Published on April 2015 | Low Power Electronics, Tunnel FET, Nanoelectronics

Improved Performance of Junctionless Tunnel Field Effect Transistor with Si and SiGe Hetero-Structure for Ultra Low Power Applications

In this paper, we present improved device characteristics of Junctionless Tunnel Field Effect Transistor (JLTFET) with Si and SiGe hetero-structure. Optimization of device is done for low power applications. Heterojunction engineering is done to optimize position of Si:SiGe junction. Subsequently, band gap engineering is incorporated using variations in, doping, gate work function, mole fraction of SiGe and dielectric constant. Comparison of optimized, hetero structure and silicon channel using numerical simulations indicates that ION increases from 0.12 to 15 µA/µm, ION/IOFF from 4×106 to 3×109 , subthreshold slope from 80 to 43mV/dec for 22nm channel with supply voltage of 0.7V.