Published on March 2014 | Low Power Electronics, Tunnel FET, Nanoelectronics

Optimal Design of High Performance H-JLTFET using HfO2 as Gate Dielectric for Ultra Low Power Applications

-In this paper we have proposed optimal design of Hetero - Junctionless Tunnel Field Effect Transistor using HfO2 as a gate dielectric. The device principle and performance are investigated in 2D simulator. During this work, we investigated the transfer characteristics, output characteristics, transconductance, Gm output conductance, GD, and C-V characteristics of our proposed device. Numerical simulations resulted in outstanding performance of H-JLFET such as ION of ~0.23mA/µm, IOFF of ~2.2×10-17A/µm, ION/IOFF of ~1013, subthreshold slope (SS) of ~12mV/dec, DIBL of ~93mV/V and Vth of ≃0.11V at room temperature and VDD of 0.7V. This indicates that H-JLTFET can play an important role for further development of low power switching applications.