Published on March 2023 | Low power Electronics, Tunnel FET, Ferroelectronics

Optimization of tunneling current in ferroelectric tunnel FET using genetic algorithm
Authors: Naima Guenifi, Shiromani Balmukund Rahi,Faiza Benmahdi,Houda Chaabane1
Journal Name: ECS Journal of Solid State Science and Technology
Volume: 12 Issue: 2 Page No: 1-8
Indexing: SCOPUS,Web of Science,Google Scholar
Abstract:

Tunnel FET is a gate-controlled, field effect transistor, followed band to band tunneling (BTBT) transport of charge carriers, having low subthreshold swing (SS < 60 Mv decade−1|T = 300 K). With tunnel FET, low-ION is a built-in problem, that limits its universal adaptability high-speed low-power uses. To overcome, this limitation of tunnel FET, a conventional double gate TFET has acquired for analysis having ferroelectric (BaTiO3)/HfO2 gate materials and source/channel region with Si1−xGex/Si semiconductor channel composition.The present device design techniques enhanced the ION and put down the subthreshold swing(SS). The analysis results by using the Silvaco simulator shows improvement in switching current(ION) approximately ∼103 times better than conventional DGTFET,without affecting the IOFF. Ultimately the change in ION∼order of 10−8 A μm−1 to 10−5 A μ has been measured for VDS ∼ 0.5 V at room temperature. The IOFF ( ∼10−20 A μm−1) has been measured. In addition to this, first time genetic algorithm has been used for the optimization of ferroelectric tunnel FET (Fe-Tunnel FET) device design parameters like a subthreshold swing (SS), ambipolar current (Iamb) and IONby using device deign parameters, doping (NS, ND), dielectric (εOX) and work function (WF).The research conclusion shows that Fe-Tunnel can play in lead backgroundfor super low power applications in advanced VLSI circuit and system.

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