Published on July 2025 | CMOS, Advanced FET

Design and Implementation of a High-Speed Level Shifter at 45nm, 90nm, and 180nm Technology Nodes using Cadence

In this work, a CMOS inverter-based level shifter in Differential Cascode Voltage Switch Logic (DCVSL) is constructed and its operation is investigated. The width and length variations of transistors at three technological nodes 45, 90, and 180 nm are compared based on the circuit behaviour. A critical analysis of the impact of supply voltage scaling on NMOS and PMOS transistors is also presented. There is also a comparison of the effects of transistor widths and lengths, as well as supply voltage variations of 1.8V, 1.5V, and 1.0V, on circuit performance. Additionally, this study compares wavelength variation and its impact on device attributes. Dynamic power, static power, energy, and delay are evaluated at the transistor and direct current levels. The Cadence Virtuoso simulation tool illustrates the variations in inverter performance under various scaling conditions. The results demonstrate that careful optimization of transistor dimensions and supply voltage can significantly enhance the performance and power efficiency of the level shifter, providing valuable insights for low-power, high-speed VLSI applications.